1. Field of the Invention
Embodiments of the invention relate generally to semiconductor memory devices. More particularly, embodiments of the invention relate to phase change memory devices and related programming methods.
A claim of priority is made to Korean Patent Application No. 2006-29692, filed on Mar. 31, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Phase change memory devices store data using phase change materials, such as chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases. The amorphous and crystalline phases (or states) exhibit different resistance values, which are used to distinguish different logic states of memory cells in the memory devices. In particular, the amorphous phase exhibits a relatively high resistance, and the crystalline phase exhibits a relatively low resistance.
At least one type of phase change memory device—phase change random access memory (PRAM)—uses the amorphous state to represent a logical “1” and the crystalline state to represent a logical “0”. In a PRAM device, the crystalline state is referred to as a “set state”, and the amorphous state is referred to as a “reset state”. Accordingly, a memory cell in a PRAM stores a logical “0” by “setting” a phase change material in the memory cell to the crystalline state, and the memory cell stores a logical “1” by “resetting” the phase change material to the amorphous state. Various PRAM devices are disclosed, for example, U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase change material in a PRAM is converted to the amorphous state by heating the material to above a predetermined melting temperature and then quickly cooling the material (See, e.g., curve “1” in FIG. 3). The phase change material is converted to the crystalline state by heating the material at another predetermined temperature below the melting temperature for a period of time (See, e.g., curve “2” in FIG. 3). Accordingly, data is written to memory cells in a PRAM by converting the phase change material in memory cells of the PRAM between the amorphous and crystalline states using heating and cooling as described.
The phase change material in a PRAM typically comprises a compound including germanium (Ge), antimony (Sb), and tellurium (Te), i.e., a “GST” compound. The GST compound is well suited for a PRAM because it can quickly transition between the amorphous and crystalline states by heating and cooling.
The memory cells in a PRAM are called “phase change memory cells”. At least one type of phase change memory cell comprises a top electrode, a chalcogenide layer, a bottom electrode contact, a bottom electrode, and an access transistor or a diode, wherein the chalcogenide layer is the phase change material for the memory cell. Accordingly, a read operation is performed on the phase change memory cell by measuring the resistance of the chalcogenide layer, and a write operation is performed on the phase change memory cell by heating and cooling the chalcogenide layer as described above.
FIG. 1 is a circuit diagram illustrating a conventional phase change memory cell 10. Referring to FIG. 1, memory cell 10 includes a phase change resistance element 11 (also labeled “GST”) comprising the GST compound, and a negative metal-oxide semiconductor (NMOS) transistor 12 (also labeled “NT”). Phase change resistance element 11 is connected between a bit line BL and NMOS transistor 12, and NMOS transistor 12 is connected between phase change resistance element 11 and ground. In addition, NMOS transistor 12 has a gate connected to a word line WL.
NMOS transistor 12 is turned on in response to a word line voltage applied to word line WL. Where NMOS transistor 12 is turned on, phase change resistance element 11 receives a current through bit line BL. Although phase change resistance element 11 is connected between bit line BL and NMOS transistor 12 in FIG. 1, phase change resistance element 11 could alternatively be connected between NMOS transistor 12 and ground.
FIG. 2 illustrates a conventional phase change memory cell 20 of a diode type PRAM. Referring to FIG. 2, memory cell 20 comprises a phase change resistance element 21 (also labeled GST) connected to a bitline BL, and a diode 22 (also labeled “D”) connected between phase change resistance element 21 and a wordline WL.
Phase change memory cell 20 is accessed by selecting wordline WL and bitline BL. In order for phase change memory cell 20 to work properly, wordline WL must have a lower voltage level than bitline BL when wordline WL is selected so that current can flow through phase change resistance element 21. Diode 22 is forward biased so that if wordline WL has a higher voltage than bitline BL, no current flows through phase change resistance element 21. To ensure that wordline WL has a lower voltage level than bitline BL, wordline WL is generally connected to ground when selected.
In FIGS. 1 and 2, phase change resistance elements 11 and 21 can alternatively be broadly referred to as “memory elements” and NMOS transistor 12 and diode 22 can alternatively be broadly referred to as “select elements”.
The operation of phase change memory cells 10 and 20 is described below with reference to FIG. 3. In particular, FIG. 3 is a graph illustrating temperature characteristics of phase change resistance elements 11 and 21 during programming operations of memory cells 10 and 20. In FIG. 3, a reference numeral “1” denotes temperature characteristics of phase change resistance elements 11 and 21 during a transition to the amorphous state, and a reference numeral “2” denotes temperature characteristics of phase change resistance elements 11 and 21 during a transition to the crystalline state.
Referring to FIG. 3, in a transition to the amorphous state, a current is applied to the GST compound in phase change resistance elements 11 and 21 for a duration T1 to increase the temperature of the GST compound above a melting temperature Tm. After duration T1, the temperature of the GST compound is rapidly decreased, or “quenched”, and the GST compound assumes the amorphous state. On the other hand, in a transition to the crystalline state, a current is applied to the GST compound in phase change resistance elements 11 and 21 for an interval T2 (T2>T1) to increase the temperature of the GST compound above a crystallization temperature Tc (Tc <Tm) for a desired period of time. After interval T2, the GST compound is slowly cooled down below the crystallization temperature so that it assumes the crystalline state.
Most phase change memory devices include a write driver circuit for supplying a program current to the GST compound in selected phase change resistance elements during programming operations. The write driver circuit typically supplies the program current with different levels depending on whether the selected phase change resistance elements are to be placed in the amorphous state or the crystalline state. Typically, a current for placing the selected phase change resistance elements in the amorphous state is referred to as a reset current and a current for placing the selected phase change resistance elements in the crystalline state is referred to as a set current. The reset and set currents are typically generated using an externally supplied power source voltage having a voltage level of at least 2.5 V.
FIG. 4 is a circuit diagram illustrating a write driver circuit 30 for a conventional phase change memory device. Write driver circuit 30 of FIG. 4 is described in detail in Korean Patent Application No. 2003-35607, which is incorporated by reference. However, for convenience, a brief description of write driver circuit 30 will be described below.
Referring to FIG. 4, write driver circuit 30 comprises a pulse control circuit 31, a current control circuit 32, and a current driving circuit 33. Pulse control circuit 31 comprises first and second transfer gates TG1 and TG2, and first through third inverters INV1 through INV3. Current control circuit 32 comprises first through seventh transistors TR1 through TR7. First through fifth transistors TR1 through TR5 are NMOS transistors and sixth and seventh transistors TR6 and TR7 are positive metal-oxide semiconductor (PMOS) transistors. Current driving circuit 33 comprises a pull-up transistor PUTR and a pull-down transistor PDTR.
Pulse control circuit 31 receives a reset pulse P_RST as an input to first transfer gate TG1, a set pulse P_SET as an input to second transfer gate TG2, and input data DATA as an input to second inverter INV2. Current control circuit 32 receives a direct current (DC) bias voltage DC_BIAS at respective gates of first and second transistors TR1 and TR2.
Where input data DATA has a logic level “0”, first transfer gate TG1 of pulse control circuit 31 is turned off, second transfer gate TG2 of pulse control circuit 31 is turned on, and third and fourth transistors TR3 and TR4 of current control circuit 32 are turned off. While second transfer gate TG2 is turned on, set pulse P_SET controls fifth transistor TR5, seventh transistor TR7, and pull-down transistor PDTR. Accordingly, where set pulse P_SET has a logic level “1”, fifth transistor TR5 turns on and seventh transistor TR7 and pull-down transistor PDTR turn off. In addition, due to a current mirror effect, a current flowing through transistors TR1, TR2, TR5 and TR6 forming a first current path causes a corresponding current to flow through pull-up transistor PUTR. The current flowing through pull-up transistor PUTR is a set current I_SET, and is provided to a memory cell MC through a data line DL.
On the other hand, where input data DATA has a logic level “1”, first transfer gate TG1 is turned on, second transfer gate TG2 is turned off, and third and fourth transistors TR3 and TR4 are turned on. While first transfer gate TG1 is turned on, reset pulse P_RST controls fifth transistor TR5, seventh transistor TR7, and pull-down transistor PDTR. Accordingly, where reset pulse P_RST has a logic level “1”, fifth transistor TR5 turns on and seventh transistor TR7 and pull-down transistor PDTR turn off. In addition, due to the current mirror effect, a current flowing through transistors TR1, TR2, TR5 and TR6 forming a first current path and a current flowing through the transistors TR3, TR4, TR5 and TR6 forming a second current path flows through a pull-up transistor PUTR. The current flowing through pull-up transistor PUTR is a reset current I_RST, and is provided to memory cell MC through data line DL.
Reset current I_RST is greater than set current I_SET and reset pulse P_RST has a smaller pulse width than set pulse P_SET. Accordingly, reset current I_RST is applied to memory cell MC with a greater magnitude, but for a shorter time, than set current I_SET. As a result, memory cell MC is programmed to the set state or the reset state in response to set pulse P_SET or reset pulse P_RST, based on the timing and temperature characteristics illustrated in FIG. 3.
As illustrated by the above descriptions, the programming of a logical “1” (i.e., a “reset programming operation”) or a logical “0” (i.e., a “set programming operation”) into memory cell MC requires control of the magnitude and duration of program currents applied to the selected cell. Write circuit 30 provides both set current I_SET and reset current I_RST to memory cell MC using current driving circuit 33. In particular, current driving circuit 33 uses a current mirror to provide set current I_SET and reset current I_RST to memory cell MC.
In the reset program operation, about 1 mA of current flows through the first current path of write driver 30, about 0.15˜0.2 mA of current flows through the second current path of write driver 30, and about 1 mA of current flows through current driving circuit 33. As a result, in the reset program operation, write driver 30 uses about 0.2 mA more current than required.